Computer Architecture

Processor, memory, and system organization.

foundation tier

Computer Architecture addresses processor, memory, and system organization. It sits within Systems and inherits that area’s core questions about correctness, scale, and tractability. This page surveys the conceptual axes of the topic and points to the references that frame ongoing research and teaching. The intent is to be useful both as an entry point for newcomers and as an index for practitioners cross-checking their mental model against the field’s primary sources.

Work on computer architecture can be organised around a few interlocking concerns: the formal objects under study, the algorithms or systems that compute over them, the resource trade-offs (time, memory, communication, statistical efficiency), and the empirical or theoretical guarantees that practitioners rely on. The sources cited below approach the topic from a mix of these angles.

Foundational references

Hennessy, Computer Architecture: A Quantitative Approach (2017) is a standard reference for this material and is used both as a curriculum anchor and as a long-form survey of techniques. Patterson, Computer Organization and Design (2020) is a standard reference for this material and is used both as a curriculum anchor and as a long-form survey of techniques.

Open methodological questions in computer architecture cluster around how to compose the techniques above under realistic constraints — scale, adversarial inputs, partial observability, and shifting workloads. The cited references give the precise statements, proofs, and empirical evaluations that this overview only sketches; downstream topic pages drill into specific subfields.

Prerequisites

Sources

  • textbook · primary · 2017
    Computer Architecture: A Quantitative Approach
    hennessy-2017
  • textbook · primary · 2020
    Computer Organization and Design
    patterson-2020

In context

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Explore

  1. 01

    Instruction Set Architectures

    RISC, CISC, x86, ARM, and RISC-V designs.
  2. 02

    Pipelining and Superscalar Execution

    Instruction-level parallelism, hazards, and out-of-order execution.
  3. 03

    Memory Hierarchy

    Caches, virtual memory, and locality.
  4. 04

    Cache Coherence

    MESI, directory-based protocols, and consistency models.
  5. 05

    Branch Prediction

    Static and dynamic predictors and TAGE-style schemes.
  6. 06

    SIMD and Vector Extensions

    AVX, NEON, and SVE for data-parallel execution.
  7. 07

    GPU Architecture

    Warps, SMs, and the modern programmable graphics pipeline.
  8. 08

    Accelerators and ASICs

    TPUs, NPUs, and domain-specific hardware for ML and DSP.
  9. 09

    FPGA and Reconfigurable Computing

    Field-programmable gate arrays and high-level synthesis.
  10. 10

    Processing-in-Memory

    Compute placed inside or near memory to reduce data movement.
  11. 11

    Neuromorphic Hardware

    Spiking and brain-inspired architectures (TrueNorth, Loihi).
  12. 12

    Energy-Efficient Computing

    DVFS, near-threshold computing, and dark silicon.
  13. 13

    Digital Logic Design

    Boolean logic, sequential circuits, and HDL design.
  14. 14

    EDA and Physical Design

    Synthesis, placement, routing, and timing closure.

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